frequency multiplier

� �� . �� , �� 50 � 100�� ,�� , �� . �� , � �� 10 sec � ��, �� 10sec �� (0.1��). �� 10sec �� display, �� , �� , ��. �� , �� . �� , �� , �� PLL . �� IC1, �� , �� 50��. �� S1 �� . �� 100, �� VCO �� IC2 4046 CMOS PLL(Phase Locked Loop-�� ). �� , �� 1�� , �� ,�� .

�� ;

�� IC1 . � �� , �� (R3-4, C5) �� VCO, �� . �� VCO �� 100 (IC1), � �� VCO, �� 100 �� , �� . � �� PLL, (� �� ), �� . �� , �� , �� , clock, �� , �� .�.

The measurement of signals of low frequency is enough difficult in enough cases. Most meters of frequency have specifications, for measurement of frequency until 50 HZ or 100HZ and the depiction, if they are drive with signals of low frequency, it does not have no precision. In order to we achieve satisfactory precision, the gate of meter should have time 10 sec or bigger, after time 10sec us gives precision of decimal digit (0.1HZ). Time of gate 10sec means that the display, will only change clue six times per minute, that makes the measurements and regulations of circuits, maddeningly. In the circuit we have a simple, but very useful multiplier of frequency. If the signals that we have we measure have noise or small time rise and dip, are necessary him we process and him we bring in the regular form of square pulse, before they are drive to the entry of PLL. This becomes with the IC1, that is a comparator, that can process signals until 50KHZ.. With the S1 we can put the circuit IN or OUT. The signal then is drive to the entry of divider via 100, between to the VCO and to the phase comparator IC2 4046 CMOS PLL(phase locked loop). With the prices that exist in the circuit, it will multiply signals of frequency, smaller of 1hZ until certain hundreds of HZ, reaching him in such regions, that can excellently be measured from any instrument.

How it works?

The pulses are applied in the entry of IC1. It produces a signal of fault, which passes from a low pass filter (R3-4, C5) and is applied in the entry of VCO, beginning the process of arrest. Because between in the exit of VCO and in the second entry of comparator is interfered divider via 100 (IC1), the frequency of VCO, will be precisely X100 of frequency of entry, when it locks. The time apprehend of PLL, (the time that is to say that is required until is achieved the locking in the signal of entry), they are certain seconds and aggrandize as long as minimizes the frequency of signal. The applications of circuit are many, where we needed proliferation of signal of low frequency, as the measurement of biological signals, clock, engines of low rotation, ect.

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